(1) Field of the Invention
The present invention relates to the field of multipliers for performing binary multiplications. More particularly, the present invention relates to parallel multiple multiplications of packed data types.
(2) Art Background
Multipliers may be implemented by software or by hardware. As well known in the art, binary multiplication involves binary digits called bits [0, 1]. Multiplication performed on binary numbers by a single bit results in either zero or the original number. Intermediate partial products generated by multiplying a multiplicand by each bit of a multiplier are added to produce the overall product. One technique of multiplication often used in a software implemented multiplier is to sum the partial products one at a time as they are generated. A drawback to such an approach is that it takes at least one machine cycle to sum each additional partial product.
In contrast, direct hardware implementations of a multiplier can yield faster processing of a multiplication operation. Even faster processing may be obtained through skipping execution cycles where an operand is composed of all zeros. Still even faster processing may be obtained by skipping the multiplications for leading bits of an operand which are all zeros and have not yet been processed.
In performing multiple multiplications in parallel, more than one multiplier is necessary. However, multipliers are very large and expensive to build. It is desirable to provide a method and apparatus for performing binary multiplication which requires relatively few multipliers and which incorporate the aforementioned feature for skipping certain multiplications or steps in multiplications which will result in pre-determined results. Such a method and apparatus are especially needed for parallel multiplications being performed on multiple packed data types which may otherwise require the use of numerous multipliers.